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Integrated Circuit Systems, Inc.
ICS950810
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application: CK-408 clock for BANIAS processor/ ODEM and MONTARA-G chipsets. Output Features: * 3 Differential CPU Clock Pairs @ 3.3V * 7 PCI (3.3V) @ 33.3MHz * 3 PCI_F (3.3V) @ 33.3MHz * 1 USB (3.3V) @ 48MHz * 1 DOT (3.3V) @ 48MHz * 1 REF (3.3V) @ 14.318MHz * 5 3V66 (3.3V) @ 66.6MHz * 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz Features: * Supports spread spectrum modulation, down spread 0 to -0.5%. (CPU, 3V66, PCI) * Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * CPU Output Skew <100ps
Pin Configuration
VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_2 3V66_3 3V66_4 3V66_5 *PD# VDDA GND Vtt_PWRGD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF FS1 FS0 CPU_STOP#* CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND VDDCPU CPUCLKT2 CPUCLKC2 MULTSEL0* IREF GND FS2 48MHz_USB 48MHz_DOT VDD48 GND 3V66_1/VCH_CLK PCI_STOP#* 3V66_0 VDD3V66 GND SCLK SDATA
56-Pin 300mil SSOP 6.10 mm. Body, 0.50 mm. pitch TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
PLL2 48MHz_USB 48MHz_DOT
Functionality
FS2 FS1 FS0 X 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU (MHz) 166.66 100.00 200.00 133.33 Tristate TCLK/2 Reserved Reserved 3V66(5:0) (MHz) 66.66 66.66 66.66 66.66 Tristate TCLK/4 Reserved Reserved PCI_F PCI (MHz) 33.33 33.33 33.33 33.33 Tristate TCLK/8 Reserved Reserved
X1 X2
XTAL OSC
3V66_5 3V66_3 3V66_(4,2)
X X X Mid Mid Mid Mid
PLL1 Spread Spectrum
REF
CPU DIVDER Stop
3 3
CPUCLKT (2:0) CPUCLKC (2:0) PCICLK (6:0) PCICLK_F (2:0) 3V66_0
PD# CPU_STOP# PCI_STOP# MULTSEL0 FS (2:0) SDATA SCLK
PCI DIVDER
Stop
7 3
Control Logic
3V66 DIVDER
Config. Reg.
3V66_1/VCH_CLK I REF
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ICS950810
ICS950810
Pin Configuration
PIN NUMBER
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
PIN NAME
VDDREF X1 X2
TYPE
PWR IN OUT
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V Cr ystal input,nominally 14.318MHz. Cr ystal output, nominally 14.318MHz.
GND
PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_2 3V66_3 3V66_4 3V66_5 PD# VDDA GND
PWR
OUT OUT OUT PWR PWR OUT OUT
Ground pin for 3V outputs.
Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power supply for PCICLK_F and PCICLK, nominal 3.3V Ground pin for 3V outputs. PCI clock outputs. PCI clock outputs.
OUT OUT PWR
PWR OUT OUT OUT PWR PWR OUT OUT OUT OUT IN PWR PWR
PCI clock outputs. PCI clock outputs.
Power supply for PCICLK_F and PCICLK, nominal 3.3V Ground pin for 3V outputs. PCI clock outputs. PCI clock outputs. PCI clock outputs. Power pin for the 3V66 clocks. Ground pin for 3V outputs. 66MHz outputs at 3.3V. 66MHz outputs at 3.3V. 66MHz outputs at 3.3V. 66MHz input/output at 3.3V. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the cr ystal are stopped. The latency of the power down will not be greater than 3ms. 3.3V power for the PLL core. Ground pin for 3V outputs.
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ICS950810
Pin Configuration (Continued)
PIN NUMBER
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
PIN NAME
Vtt_PWRGD# SDATA SCLK GND VDD3V66 3V66_0 PCI_STOP# 3V66_1/VCH_CLK GND VDD48 48MHz_DOT 48MHz_USB FS2 GND IREF MULTSEL0 CPUCLKC2 CPUCLKT2 VDDCPU GND CPUCLKC1 CPUCLKT1 VDDCPU CPUCLKC0 CPUCLKT0 CPU_STOP# FS0 FS1 REF
TYPE
IN I/O IN PWR PWR OUT IN OUT PWR PWR OUT OUT IN PWR OUT IN OUT OUT PWR PWR OUT OUT PWR OUT OUT IN IN IN OUT
DESCRIPTION
This 3.3V LVTTL input is a level sensitive strobe used to deter mine when FS[2:0] and MULTISEL0 inputs are valid and are ready to be sampled. (active low) Data pin for I2C circuitr y 5V tolerant Clock pin of I2C circuitr y 5V tolerant Ground pin for 3V outputs. Power pin for the 3V66 clocks. 66MHz outputs at 3.3V. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when i n p u t l ow Selectable 48MHz non-SSC or 66MHz SSC clock output Ground pin for 3V outputs. Power for 48MHz output buffers and fixed PLL core. 48MHz output clock 48MHz output clock Frequency select pin. Ground pin for 3V outputs. This pin festablishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropr iate current. 3.3V LVTTL input for selection the current multiplier for CPU outputs "Complementar y" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. "Tr ue" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. Supply for CPU clocks,3.3V nominal Ground pin for 3V outputs. "Complementar y" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. "Tr ue" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. Supply for CPU clocks,3.3V nominal "Complementar y" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. "Tr ue" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. This asynchronous input halts to active low level when dr iven low. Frequency select pin. Frequency select pin. 14.318 MHz reference clock.
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ICS950810
Power Groups
(Analog) VDDA = PLL1 VDD48 = 48MHz, PLL VDDREF = VDD for Xtal, POR
(Digital) VDDPCI VDD3V66 VDDCPU
Truth Table
FS2 X X X X Mid Mid Mid Mid FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU (MHz) 166.66 100.00 200.00 133.33 Tristate TCLK/2 3V66 (5:0) (MHz) 66.66 66.66 66.66 66.66 Tristate TCLK/4 PCI_F PCI (MHz) 33.33 33.33 33.33 33.33 Tristate TCLK/8 Reserved Reserved REF0 (MHz) 14.318 14.318 14.318 14.318 Tristate TCLK Reserved Reserved USB/DOT (MHz) 48.00 48.00 48.00 48.00 Tristate TCLK/2 Reserved Reserved
Reserved Reserved Reserved Reserved
Maximum Allowed Current
Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 25mA 360mA
Condition Powerdown Mode (PWRDWN# = 0) Full Active
Host Swing Select Functions
MULTISEL0 0 1 Board Target Trace/Term Z 50 ohms Reference R, Iref = VDD/(3*Rr) Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 6* I REF Voh @ Z 0.7V @ 50
NOTE: MULTSEL0 = 0 not supported in ICS950810. Refer to ICS950805 for Buffered Mode support.
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ICS950810
Power Management
PD# 0 1 1 1 1 CPU_STOP# X 1 0 1 1 PCI_STOP# X 1 1 0 1 VCO STOP RUN RUN RUN RUN CPU Iref*2 RUN Iref*2 RUN RUN CPU# FLOAT RUN FLOAT RUN RUN PCICLK LOW RUN RUN LOW RUN 3v66 LOW RUN RUN RUN RUN 48MHz LOW RUN RUN RUN RUN REF LOW RUN RUN RUN RUN
Note: PCI_F is not affected by PCI_STOP# and CPU_STOP#
Tri-State Control of CPU Outputs
State 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Byte0 bit6 Byte1bit6 PD# Cpu_stop# 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 Pin PD# 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Pin Stoppable Cpu_Stop# CPU outputs 1 Running 0 Irefx6 1 Irefx2 0 Irefx2 1 Running 0 Hi-Z 1 Hi-Z 0 Hi-Z 1 Running 0 Irefx6 1 Hi-Z 0 Hi-Z 1 Running 0 Hi-Z 1 Hi-Z 0 Hi-Z Free-Running CPU outputs Running Running Irefx2 Irefx2 Running Running Irefx2 Irefx2 Running Running Hi-Z Hi-Z Running Running Hi-Z Hi-Z
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ICS950810
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +85C Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS VIH Input High Voltage VIL Input Low Voltage IIH VIN = VDD Input High Current VIN = 0 V; Inputs with no pull-up IIL1 resistors Input Low Current VIN = 0 V; Inputs with pull-up IIL2 resistors IDD3.3OP Operating Supply Current IDD3.3OP Powerdown Current Input Frequency Pin Inductance Input Capacitance1 Clk Stabilization1,2
1
MIN 2 VSS -0.3 -5 -5 -200 229 220
TYP
MAX VDD +0.3 0.8 5
UNITS V V
A
CL = Full load; Select @ 100 MHz CL =Full load; Select @ 133 MHz IREF=2.32 mA VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From PowerUp or deassertion of PowerDown to 1st clock. Output enable delay (all outputs) Output disable delay (all outputs)
230 233 22 14.318
360 360 25 7 5 6 45 1.8 10 10
mA mA mA MHz nH pF pF pF ms ns ns
IDD3.3PD Fi Lpin CIN COUT CINX TSTAB tPZH,tPZL
27
30 1
1 1
Delay
1 2
tPHZ,tPLZ
Guaranteed by design, not 100% tested in production. See timing diagrams for buffered and un-buffered timing requirements.
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ICS950810
Electrical Characteristics - CPU (0.7V Select)
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Current Source Output 1 VO = Vx Zo Impedance Statistical measurement on Voltage High VHigh single ended signal using Voltage Low VLow Measurement on single ended Max Voltage Vovs signal using absolute value. Min Voltage Vuds Crossing Voltage (abs) Vcross(abs) Variation of crossing over all Crossing Voltage (var) d-Vcross edges Rise Time tr V OL = 0.175V, V OH = 0.525V V OH = 0.525V V OL = 0.175V Fall Time tf Rise Time Variation d-tr Fall Time Variation d-tf Measurement from differential Duty Cycle dt3 wavefrom V T = 50% Skew tsk3 Jitter, Cycle to cycle
1 2
MIN 3000 660 -150 -450 250
TYP
MAX
UNITS
810 20 850 -15 380 22
850 150 1150 550 140 700 700 125 125 55 100 150
mV mV mV mV ps ps ps ps % ps ps
175 175
290 310 10 10 51 16 48
45
tjcyc-cyc 1
V T = 50%
Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance V O = V DD*(0.5) RDSP1 Output High Voltage IOH = -1 mA VOH1 Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc
1
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33 3.28 0.08 -110 -20 110 37 1.28 1.37 51.1 127 164
MAX 55 0.55 -33 38 2 2 55 500 250
UNITS W V V mA mA ns ns % ps ps
VOL1 IOH1 IOL1 tr1
1
IOL = 1 mA V
OH@MIN = 1.0 V
V OH@MAX = 3.135 V VOL @MIN = 1.95 V V OL @MAX = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, V OL = 0.4 V V T = 1.5 V V T = 1.5 V V T = 1.5 V
tf11 dt11 tsk11 tjcyc-cyc 1
Guaranteed by design, not 100% tested in production.
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ICS950810
Electrical Characteristics - 3V66 Mode: 3V66 [5:0]
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL V OH@MIN = 1.0 V 1 Output High Current IOH V OH@MAX = 3.135 V VOL @MIN = 1.95 V 1 Output Low Current IOL VOL @MAX = 0.4 V 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 VT = 1.5 V Duty Cycle dt1 Skew Jitter
1
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33 3.28 0.08 -110 -20 110 37 1.15 1.53 51.3 67 175
MAX 55 0.55 -33 38 2 2 55 250 250
UNITS V V mA mA ns ns % ps ps
tsk1
1
VT = 1.5 V VT = 1.5 V 3V66
1 tjcyc-cyc
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL V OH@MIN = 1.0 V 1 Output High Current IOH V OH@MAX = 3.135 V VOL @MIN = 1.95 V 1 Output Low Current IOL VOL @MAX = 0.4 V 1 VOL = 0.4 V, VOH = 2.4 V 48DOT Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V 48DOT Fall Time tf1 1 VOL = 0.4 V, VOH = 2.4 V VCH 48 USB Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V VCH 48 USB Fall Time tf1 48 DOT Duty Cycle VCH 48 USB Duty Cycle 48 DOT Jitter 48 USB Jitter USB to DOT Skew VCH Jitter
1
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MIN 20 2.4 -29 29 0.5 0.5 1 1 45 45
TYP 48 3.27 0.08 -61 -12
MAX 60 0.4 -23 27 1 1 2 2 55 55 350 350 1 350
UNITS V V mA mA ns ns ns ns % % ps ps ns ps
dt1 dt1
1 1
VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V (0 OR 180 degrees) VT = 1.5 V
0.69 0.81 1.37 1.47 51.2 53.5 111 99 147
1 tjcyc-cyc 1 tjcyc-cyc 1 tsk1 1 tjcyc-cyc
Guaranteed by design, not 100% tested in production.
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ICS950810
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL V OH@MIN = 1.0 V 1 Output High Current IOH V OH@MAX = 3.135 V VOL @MIN = 1.95 V 1 Output Low Current IOL VOL @MAX = 0.4 V 1 VOL = 0.4 V, VOH = 2.4 V Rise Time tr1 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 VT = 1.5 V Duty Cycle dt1 Jitter
1
MIN 20 2.4 -33 30 1 1 45
TYP 48 3.28 0.08 -110 -20 110 37 1.69 1.56 53 152
MAX 60 0.4 -33 38 2 2 55 1000
UNITS V V mA mA ns ns % ps
tjcyc-cyc
1
VT = 1.5 V
Guaranteed by design, not 100% tested in production.
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ICS950810
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
ACK
Byte 1
Byte 1
ACK
ACK
Byte 2
Byte 2
ACK
ACK
Byte 3
Byte 3
ACK
ACK
Byte 4
Byte 4
ACK
ACK
Byte 5
Byte 5
ACK
ACK
Byte 6
Byte 6
ACK
ACK Stop Bit
Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS950810
I2C Tables
BYTE 0 Bit 7 Pin # Affected Pin Name Spread Enabled Control Function Type RW Bit Control 0 1 OFF ON PWD 0
Bit 6
-
CPU_T(2:0)
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
35 53 34 40 55 54
3V66_1/VCH_CLK CPU_STOP#* PCI_STOP#* FS2 FS1 FS0
Spread Spectrum Control Power down mode output level 0= CPU driven in power RW down 1= undriven VCH/66.66 Select RW Reflects value of pin R Reflects value of pin at R/RW power up. Also can be set. Frequency Selection RW Frequency Selection RW Frequency Selection RW
HIGH
LOW
0
66.66 Stop Stop -
48.00 Active Active -
0 X 1 X X X
BYTE 1 Bit 7
Pin # 43
Affected Pin Name MULTSEL0*
Control Function Reflects value of pin
Type R
Bit Control 0 1 -
PWD x
Bit 6
-
CPU_T(2:0)
CPU_Stop mode output level 0= CPU driven when stopped RW 1 = undriven Allow control of output with assertion of CPU_STOP#. Allow control of output with assertion of CPU_STOP#. Allow control of output with assertion of CPU_STOP#. Output control Output control Output control RW RW RW RW RW RW
HIGH
LOW
0
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
45, 44 49, 48 52, 51 45, 44 49, 48 52, 51
CPUCLKT2 CPUCLKC2 CPUCLKT1 CPUCLKC1 CPUCLKT0 CPUCLKC0 CPUCLKT2 CPUCLKC2 CPUCLKT1 CPUCLKC1 CPUCLKT2 CPUCLKC2
Not Freerun Freerun Not Freerun Freerun Not Freerun Freerun Disable Enable Disable Enable Disable Enable
0 0 0 1 1 1
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ICS950810
BYTE 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # 18 17 16 13 12 11 10
Affected Pin Name PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Control Function (Reserved) Output control Output control Output control Output control Output control Output control Output control
Type RW RW RW RW RW RW RW
Bit Control 0 1 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable
PWD 0 1 1 1 1 1 1 1
BYTE 3 Bit 7 Bit 6 Bit 5
Affected Pin Pin # 38 39 7 Name 48MHz_DOT 48MHz_USB PCICLK_F2
Control Function Output control Output control Allow control of output with assertion of PCI_STOP#. Allow control of output with assertion of PCI_STOP#. Allow control of output with assertion of PCI_STOP#. Output control Output control Output control
Type RW RW RW
Bit Control 0 1 Disable Enable Disable Enable Freerun Not Freerun Not Freerun Not Freerun PWD 1 1 0
Bit 4
6
PCICLK_F1
RW
Freerun
0
Bit 3 Bit 2 Bit 1 Bit 0
5 7 6 5
PCICLK_F0 PCICLK_F2 PCICLK_F1 PCICLK_F0
RW RW RW RW
Freerun
0 1 1 1
Disable Enable Disable Enable Disable Enable
BYTE 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # 33 35 24 23 22 21
Affected Pin Name 3V66_0 3V66_1/VCH_CLK 3V66_5 3V66_4 3V66_3 3V66_2
Control Function (Reserved) (Reserved) Output control Output control Output control Output control Output control Output control
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable
PWD 0 0 1 1 1 1 1 1
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ICS950810
BYTE 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # X X X X X X X X
Affected Pin Name -
Control Function (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Type -
Bit Control 0 1 -
PWD 0 0 0 0 0 0 0 0
BYTE 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # X X X X X X X X
Affected Pin Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0
Control Function (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Type R R R R R R R R
Bit Control 0 1 -
PWD 1 1 1 1 1 1 1 1
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3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) Tpci
Skews at Common Transition Edges
GROUP PCI 3V66 3V66 to PCI
1
SYMBOL PCI tsk1 3V66 tsk1 S3V66-PCI
CONDITIONS VT = 1.5 V VT = 1.5 V 3V66 (5:0) leads 33MHz PCI
MIN
TYP 127 67
1.5
MAX 500 250 3.5
UNITS ps ps ns
Guarenteed by design, not 100% tested in production.
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CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0' the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not be driven . When the I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU and CPU# outputs will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUT CPUC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
CPU_STOP# - De-assertion (transition from logic "0" to logic "1") All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the de-assertion to active outputs is to be defined to be tetween 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 3 nS of CPU_Stop# de-assertion.
De-assertion of CPU_STOP# Waveforms
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ICS950810
PD# - Assertion (transition from logic "1" to logic "0") When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Power Down Assertion of Waveforms
0ns PD # CPUT 100MHz CPUC 100MHz 3V66MHz PCI 33MHz USB 48MHz REF 14.318MHz 25ns 50ns
Power Down De-Assertion Mode The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping of the power supply until the time that stable clocks are output from the clock chip. If the I2C Bit 6 of Byte 0 is programmed to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
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ICS950810
PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_S TOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz
tsu
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ICS950810
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
10-0034
D (inch) MIN .720 MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950810yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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ICS950810
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 56
10-0039
-Ce
b SEATING PLANE
D mm. MIN 13.90 MAX 14.10 MIN .547
D (inch) MAX .555
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
(240 mil)
6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil)
Ordering Information
ICS950810yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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